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ABRIDGED DATA SHEET Rev: 101708
DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip
General Description
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. TDM data is transported in up to 64 individually configurable bundles. All standardsbased TDM-over-packet mapping methods are supported except AAL2. Frame-based serial HDLC data flows are also supported. The high level of integration available with the DS34S10x devices minimizes cost, board space, and time to market.
Features
Transport of E1, T1, E3, T3 or STS-1 TDM or CBR Serial Signals Over Packet Networks Full Support for These Mapping Methods: SAToP, CESoPSN, TDMoIP (AAL1), HDLC, Unstructured, Structured, Structured with CAS Adaptive Clock Recovery, Common Clock, External Clock and Loopback Timing Modes On-Chip TDM Clock Recovery Machines, One Per Port, Independently Configurable Clock Recovery Algorithm Handles Network PDV, Packet Loss, Constant Delay Changes, Frequency Changes and Other Impairments 64 Independent Bundles/Connections Multiprotocol Encapsulation Supports IPv4, IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet VLAN Support According to 802.1p and 802.1Q 10/100 Ethernet MAC Supports MII/RMII/SSMII Selectable 32-Bit, 16-Bit or SPI Processor Bus Operates from Only Two Clock Signals, One for Clock Recovery and One for Packet Processing Glueless SDRAM Buffer Management Low-Power 1.8V Core, 3.3V I/O
Applications
TDM Circuit Extension Over PSN o Leased-Line Services Over PSN o TDM Over GPON/EPON o TDM Over Cable o TDM Over Wireless Cellular Backhaul Over PSN Multiservice Over Unified PSN HDLC-Based Traffic Transport Over PSN

See detailed feature list in Section 5 .
Functional Diagram
CPU Bus
Ordering Information
PART DS34S101GN * DS34S101GN+* DS34S102GN* DS34S102GN+* DS34S104GN DS34S104GN+ DS34S108GN DS34S108GN+ PORTS TEMP RANGE 1 1 2 2 4 4 8 8 -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 256 TECSBGA 256 TECSBGA 256 TECSBGA 256 TECSBGA 256 TECSBGA 256 TECSBGA 484 HSBGA 484 HSBGA
DS34S108
TDM Interfaces Circuit Emulation Engine 10/100 Ethernet MAC xMII Interface
Manager
Buffer
Clock
Adapters
SDRAM Interface
Clock Inputs
+Denotes lead-free/RoHS-compliant package (explanation). *Future product--contact factory for availability.
________________________________________________________ Maxim Integrated Products
1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
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1 Applicable Standards
Table 1-1. Applicable Standards SPECIFICATION IEEE IEEE 802.3 IEEE 1149.1 IETF RFC 4553 RFC 4618 RFC 5086 RFC 5087 ITU-T G.823 G.824 G.8261/Y.1361 I.363.1 I.363.2 I.366.2 O.151 O.161 Y.1413 Y.1414 Y.1452 Y.1453 MEF MEF 8 MFA MFA 4.0 MFA 5.0.0 MFA 8.0.0 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications (2005) Standard Test Access Port and Boundary-Scan Architecture, 1990 Structure-Agnostic Time Division Multiplexing (TDM) over Packet (SAToP) (06/2006) Encapsulation Methods for Transport of PPP/High-Level Data Link Control (HDLC) over MPLS Networks (09/2006) Structure-Aware Time Division Multiplexed (TDM) Circuit Emulation Service over Packet Switched Network (CESoPSN) (12/2007) Time Division Multiplexing over IP (TDMoIP) (12/2007) The Control of Jitter and Wander within Digital Networks which are Based on the 2048kbps Hierarchy (03/2000) The Control of Jitter and Wander within Digital Networks which are Based on the 1544kbps Hierarchy (03/2000) Timing and Synchronization Aspects in Packet Networks (05/2006) B-ISDN ATM Adaptation Layer Specification: Type 1 AAL (08/1996) B-ISDN ATM Adaptation Layer Specification: Type 2 AAL (11/2000) AAL Type 2 Service Specific Convergence Sublayer for Narrow-Band Services (11/2000) Error Performance Measuring Equipment Operating at the Primary Rate and Above (1992) In-Service Code Violation Monitors for Digital Systems (1993) TDM-MPLS Network Interworking - User Plane Interworking (03/2004) Voice Services-MPLS Network Interworking (07/2004) Voice Trunking over IP Networks (03/2006) TDM-IP Interworking - User Plane Networking (03/2006) Implementation Agreement for the Emulation of PDH Circuits over Metro Ethernet Networks (10/2004) TDM Transport over MPLS Using AAL1 (06/2003) I.366.2 Voice Trunking Format over MPLS Implementation Agreement (08/2003) Emulation of TDM Circuits over MPLS Using Raw Encapsulation - Implementation Agreement (11/2004) SPECIFICATION TITLE
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2 Detailed Description
The DS34S108 is an 8-port TDM-over-Packet (TDMoP) IC. The DS34S104, DS34S102 and DS34S101 have the same functionality as the DS34S108, except they have only 4, 2 or 1 ports, respectively. These sophisticated devices can map and demap multiple E1/T1 data streams or a single E3/T3/STS-1 data stream to and from IP, MPLS or Ethernet networks. A built-in MAC supports connectivity to a single 10/100 Mbps PHY over an MII, RMII or SSMII interface. The DS34S10x devices are controlled through a 16 or 32-bit parallel bus interface or a highspeed SPI serial interface. The TDM-over-Packet (TDMoP) core is the enabling block for circuit emulation and other network applications. It performs transparent transport of legacy TDM traffic over Packet Switched-Networks (PSN). The TDMoP core implements payload mapping methods such as AAL1 for circuit emulation, HDLC method, structure-agnostic SAToP method, and the structure-aware CESoPSN method. The AAL1 payload-type machine maps and demaps E1, T1, E3, T3, STS-1 and other serial data flows into and out of IP, MPLS or Ethernet packets, according to the methods described in ITU-T Y.1413, Y.1453, MEF 8, MFA 4.1 and IETF RFC 5087 (TDMoIP). It supports E1/T1 structured mode with or without CAS, using a timeslot size of 8 bits, or unstructured mode (carrying serial interfaces, unframed E1/T1 or E3/T3/STS-1 traffic). The HDLC payload-type machine maps and demaps HDLC dataflows into and out of IP/MPLS packets according to IETF RFC 4618 (excluding clause 5.3 - PPP) and IETF RFC 5087 (TDMoIP). It supports 2-, 7- and 8-bit timeslot resolution (i.e. 16, 56, and 64 kbps respectively), as well as N x 64 kbps bundles (n=1 to 32). Supported applications of this machine include trunking of HDLC-based traffic (such as Frame Relay) implementing Dynamic Bandwidth Allocation over IP/MPLS networks and HDLC-based signaling interpretation (such as ISDN D-channel signaling termination - BRI or PRI, V5.1/2, or GR-303). The SAToP payload-type machine maps and demaps unframed E1, T1, E3 or T3 data flows into and out of IP, MPLS or Ethernet packets according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 4553. It supports E1/T1/E3/T3 with no regard for the TDM structure. If TDM structure exists it is ignored, allowing this to be the simplest mapping/demapping method. The size of the payload is programmable for different services. This emulation suits applications where the provider edges have no need to interpret TDM data or to participate in the TDM signaling. The PSN network must have almost no packet loss and very low packet delay variation (PDV) for this method. The CESoPSN payload-type machine maps and demaps structured E1, T1, E3 or T3 data flows into and out of IP, MPLS or Ethernet packets with static assignment of timeslots inside a bundle according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and the IETF RFC 5086 (CESoPSN). It supports E1/T1/E3/T3 while taking into account the TDM structure. The level of structure must be chosen for proper payload conversion such as the framing type (i.e. frame or multiframe). This method is less sensitive to PSN impairments but lost packets could still cause service interruption.
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3 Application Examples
In Figure 3-1, a DS34S10x device is used in each TDMoP gateway to map TDM services into a packet-switched metropolitan network. TDMoP data is carried over various media: fiber, wireless, G/EPON, coax, etc. Figure 3-1. TDMoP in a Metropolitan Packet Switched Network
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Figure 3-2. TDMoP in Cellular Backhaul
Other Possible Applications
Point-to-Multipoint TDM Connectivity over IP/Ethernet
The DS34S10x devices support NxDS0 TDMoP connections (known as bundles) with or without CAS (Channel Associated Signaling). There is no need for an external TDM cross-connect, since the packet domain can be used as a virtual cross-connect. Any bundle of timeslots can be directed to another remote location on the packet domain.
HDLC Transport over IP/MPLS
TDM traffic streams often contain HDLC-based control channels and data traffic. These data streams, when transported over a packet domain, should be treated differently than the time-sensitive TDM payload. DS34S10x devices can terminate HDLC channels in the TDM streams and optionally map them into IP/MPLS/Ethernet for transport. All HDLC-based control protocols (ISDN BRI and PRI, SS7 etc.) and all HDLC data traffic can be managed and transported.
Using a Packet Backplane for Multiservice Concentrators
A communications device with all the above-mentioned capabilities can use a packet-based backplane instead of the more expensive TDM bus option. This enables a cost-effective and future-proof design of communication platforms with full support for both legacy and next-generation services.
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4 Block Diagram
Figure 4-1. Top-Level Block Diagram
SD_D[31:0] SD_DQM[3:0] SD_A[11:0] SD_BA[1:0] SD_CLK SD_CS_N SD_WE_N SD_RAS_N SD_CAS_N
CLK_HIGH
CLK_CMN
CLAD1
38.88MHz 2.048 /1.544 MHz
TDMoP Block
all 8 ports TDMn_ACLK TDMn_TX TDMn_TCLK TDMn_TX_SYNC TDMn_TX_MF_CD TDMn_TSIG_CTS Timeslot Assigner Clock Recovery Machines Payload Type Machines RAW SAToP CESoPSN Jitter Buffer Control SDRAM Controller
Data Byte Enable Mask Address Bank Select Control
CLAD2
50 or 75MHz
CLK_SYS_S CLK_SYS
AAL1 HDLC Packet Classifier
TDMn_RCLK TDMn_RX TDMn_RX_SYNC TDMn_RSIG_RTS CAS Handler
Ethernet MAC 10/100
MII_TX_ERR MII_TX_EN MII_TXD[3:0] CLK_SSMII _TX CLK_MII_TX MII_CRS MII_COL MII_RX_ERR MII_RX_DV MII_RXD[3:0] CLK_MII_RX MDIO MDC
Counters & Status Registers
Queue Manager
CPU Interface
JTAG
SCAN MBIST
JTMS JTCLK JTDI JTDO JTRST_N
HIZ_EN SCEN STMD MBIST_EN MBIST_DONE MBIST_FAIL
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H_CS_N H_R_W_N H_WR_BE[0]_N / SPI _CLK H_WR_BE[1]_N / SPI_MOSI H_WR_BE[2]_N / SPI_SEL_N H_WR_BE[3]_N / SPI_CI H_READY_N H_INT[1:0]
H_CPU_SPI_N DATA_31_16_N
H_D[0] / SPI_MISO
RST_SYS_N
H_AD[24:1]
H_D[31:1]
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5 Features
Global Features
* TDMoP Interfaces o DS34S101: 1 E1/T1/serial TDM interface o DS34S102: 2 E1/T1/serial TDM interfaces o DS34S104: 4 E1/T1/serial TDM interfaces o DS34S108: 8 E1/T1/serial TDM interfaces o All four devices: optionally 1 high-speed E3/DS3/STS-1 TDM interface o All four devices: each interface optionally configurable for serial operation for V.35 and RS530 Ethernet Interface o One 10/100 Mbps port configurable for MII, RMII or SSMII interface format o Half or full duplex operation o VLAN support according to 802.1p and 802.1Q including stacked tags o Fully compatible with IEEE 802.3 standard End-to-end TDM synchronization through the IP/MPLS domain by on-chip, per-port TDM clock recovery 64 independent bundles/connections, each with its own: o Transmit and receive queues o Configurable jitter-buffer depth o Connection-level redundancy, with traffic duplication option Packet loss compensation and handling of misordered packets Glueless SDRAM interface Complies with MPLS-Frame Relay Alliance Implementation Agreements 4.1, 5.1 and 8.0 Complies with ITU-T standards Y.1413 and Y.1414. Complies with Metro Ethernet Forum 3 and 8 Complies with IETF RFC 4553 (SAToP), RFC 5086 (CESoPSN) and RFC 5087 (TDMoIP) IEEE 1146.1 JTAG boundary scan 1.8V and 3.3V Operation with 5.0V tolerant I/O
*
* *
* * * * * * * *
Clock Synthesizers
* * Clocks to operate the TDMoP clock recovery machines can synthesized from a single clock input (10MHz, 19.44MHz, 38.88MHz or 77.76MHz on the CLK_HIGH pin) Clock to operate TDMoP logic and SDRAM interface (50MHz or 75MHz) can be synthesized from a single 25MHz clock on the CLK_SYS pin
TDM-over-Packet Block
* * * * Enables transport of TDM services (E1, T1, E3, T3, STS-1) or serial data over packet-switched networks SAToP payload-type machine maps/demaps unframed E1/T1/E3/T3/STS-1 or serial data flows to/from IP, MPLS or Ethernet packets according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 4553. CESoPSN payload-type machine maps/demaps structured E1/T1 data flows to/from IP, MPLS or Ethernet packets with static assignment of timeslots inside a bundle according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0 and IETF RFC 5086. AAL1 payload-type machine maps/demaps E1/T1/E3/T3/STS-1 or serial data flows to/from IP, MPLS or Ethernet packets according to ITU-T Y.1413, MEF 8, MFA 4.1 and IETF RFC 5087. For E1/T1 it supports structured mode with/without CAS using 8-bit timeslot resolution, while implementing static timeslot allocation. For E1/T1, E3/T3/STS-1 or serial interface it supports unstructured mode. HDLC payload-type machine maps/demaps HDLC-based E1/T1/serial flow to/from IP, MPLS or Ethernet packets. It supports 2-, 7- and 8-bit timeslot resolution (i.e. 16, 56, and 64 kbps respectively), as well as N x 64 kbps bundles. This is useful in applications where HDLC-based signaling interpretation is required (such as ISDN D channel signaling termination, V.51/2, or GR-303), or for trunking packet-based applications (such as Frame Relay), according to IETF RFC 4618. 7 of 13
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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108 TDMoP TDM Interfaces
* * * Supports single high-speed E3, T3 or STS-1 interface on port 1 or one (DS34S101), two (DS34S102), four (DS34S104) or eight (DS34S108) E1, T1 or serial interfaces For single high-speed E3, T3 or STS-1 interface, AAL1 or SAToP payload type is used For E1 or T1 interfaces, the following modes are available: o Unframed - E1/T1 pass-through mode (AAL1, SAToP or HDLC payload type) o Structured - fractional E1/T1 support (all payloads) o Structured with CAS - fractional E1/T1 with CAS support (CESoPSN or AAL1 payload type) For serial interfaces, the following modes are available: o Arbitrary continuous bit stream (using AAL1 or SAToP payload type) o Single-interface high-speed mode on port 1 up to STS-1 rate (51.84 Mbps) using a single bundle/connection. o Low-speed mode with each interface operating at N x 64 kbps (N = 1 to 63) with an aggregate rate of 18.6Mbps o HDLC-based traffic (such as Frame Relay) at N x 64 kbps (N = 1 to 63) with an aggregate rate of 18.6Mbps). All serial interface modes are capable of working with a gapped clock.
*
*
TDMoP Bundles
* * * * * * * 64 independent bundles, each can be assigned to any TDM interface Each bundle carries a data stream from one TDM interface over IP/MPLS/Ethernet PSN from TDMoP source device to TDMoP destination device Each bundle may be for N x 64kbps, an entire E1, T1, E3, T3 or STS-1, or an arbitrary serial data stream Each bundle is uni-directional (but frequently coupled with opposite-direction bundle for bidirectional communication) Multiple bundles can be transported between TDMoP devices Multiple bundles can be assigned to the same TDM interface Each bundle is independently configured with its own: o Transmit and receive queues o Configurable receive-buffer depth o Optional connection-level redundancy (SAToP, AAL1, CESoPSN only). Each bundle can be assigned to one of the payload-type machines or to the CPU For E1/T1 the device provides internal bundle cross-connect functionality, with DS0 resolution
* *
TDMoP Clock Recovery
* * Sophisticated TDM clock recovery machines, one for each TDM interface, allow end-to-end TDM clock synchronization, despite the packet delay variation of the IP/MPLS/Ethernet network The following clock recovery modes are supported: o Adaptive clock recovery o Common clock (using RTP) o External clock o Loopback clock The clock recovery machines provide both fast frequency acquisition and highly accurate phase tracking: o Jitter and wander of the recovered clock are maintained at levels that conform to G.823/G.824 traffic or synchronization interfaces. (For adaptive clock recovery, the recovered clock performance depends on packet network characteristics.) o Short-term frequency accuracy (1 second) is better than 16 ppb (using OCXO reference), or 100 ppb (using TCXO reference) o Capture range is 90 ppm o Internal synthesizer frequency resolution of 0.5 ppb o High resilience to packet loss and misordering, up to 2% without degradation of clock recovery performance o Robust to sudden significant constant delay changes 8 of 13
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o Automatic transition to holdover when link break is detected
TDMoP Delay Variation Compensation
* * Configurable jitter buffers compensate for delay variation introduce by the IP/MPLS/Ethernet network Large maximum jitter buffer depths: o E1: up to 256 ms o T1 unframed: up to 340 ms o T1 framed: up to 256 ms o T1 framed with CAS: up to 192 ms o E3: up to 60 ms o T3: up to 45 ms o STS-1: up to 40 ms. Packet reordering is performed for SAToP and CESoPSN bundles within the range of the jitter buffer Packet loss is compensated by inserting either a pre-configured conditioning value or the last received value.
* *
TDMoP CAS Support
* * On-chip CAS handler terminates E1/T1 CAS when using AAL1/CESoPSN in structured-with-CAS mode. CPU intervention is not required for CAS handling.
Test and Diagnostics
* * IEEE 1149.1 JTAG support MBIST (memory built-in self test)
CPU Interface
* * * * * * * 32 or 16-bit parallel interface or optional SPI serial interface Byte write enable pins for single-byte write resolution Hardware reset pin Software reset supported Software access to device ID and silicon revision On-chip SDRAM controller provides access to SDRAM for both the chip and the CPU CPU can access transmit and receive buffers in SDRAM used for packets to/from the CPU (ARP, SNMP, etc.)
6 Overview of Major Operational Modes
Globally, the resources of the device can be committed to either one high-speed E3, T3 or STS-1 TDM stream (high-speed mode) or one or more E1, T1 or serial streams (normal low-speed mode). In high-speed mode, the TDM signal is carried using an unstructured AAL1 or SAToP mapping. High-speed mode is enabled by setting General_cfg_reg0.High_speed=1. In normal, low-speed mode, each port can be configured for E1, T1 or serial (e.g. V.35) operation. Ports configured for E1 or T1 can be further configured for unframed, framed, or multiframed interface. In addition, each port can be configured to have the transmit and receive directions clocked by independent clocks (two-clock mode) or to have both directions clocked by the transmit clock (one-clock mode). All of this configuration is specified in the per-port Port[n]_cfg_reg register.
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7 Pin Descriptions
7.1 Short Pin Descriptions
Table 7-1. Short Pin Descriptions PIN NAME TYPE TDM Interface
TDMn_ACLK TDMn_TCLK TDMn_TX TDMn_TX_SYNC TDMn_TX_MF_CD TDMn_TSIG_CTS TDMn_RCLK TDMn_RX TDMn_RX_SYNC TDMn_RSIG_RTS O Ipu O Ipd IOpd O Ipu Ipu Ipd Ipu O IO O O O O O O O I O O O O I I I I I I O IOpu I I I I Ipu Ipu IO IO I I I I I
PIN DESCRIPTION
TDMoP Recovered Clock Output TDMoP Transmit Clock Input (here transmit means "away from Ethernet MII") TDMoP Transmit Data Output TDMoP Transmit Frame Sync Input TDMoP Transmit Multiframe Sync Input or Carrier Detect Output TDMoP Transmit Signaling Output or Clear to Send Output TDMoP Receive Clock Input (here receive means "toward Ethernet MII") TDMoP Receive Data Input TDMoP Receive Frame/Multiframe Sync Input TDMoP Receive Signaling Input or Request To Send Input SDRAM Clock SDRAM Data Bus SDRAM Byte Enable Mask SDRAM Address Bus SDRAM Bank Select Outputs SDRAM Chip Select (Active Low) SDRAM Write Enable (Active Low) SDRAM Row Address Strobe (Active Low) SDRAM Column Address Strobe (Active Low) MII Transmit Clock Input SSMII Transmit Clock Output MII Transmit Data Outputs MII Transmit Enable Output MII Transmit Error Output MII Receive Clock Input MII Receive Data Inputs MII Receive Data Valid Input MII Receive Error Input MII Collision Input MII Carrier Sense Input PHY Management Clock Output PHY Management Data Input/Output System Clock Selection Input System Clock Input: 25, 50 or 75MHz Common Clock Input (for common clock mode also known as differential mode) Clock High Input (for adaptive clock recovery machines and E1/T1 master clocks) Host Bus Interface (1=Parallel Bus, 0=SPI Bus) Data Bus Width (1=32-bit , 0=16-bit) Host Data Bus Host Data LSb or SPI Data Output Host Address Bus Host Chip Select (Active Low) Host Read/Write Control or SPI Clock Phase Host Write Enable Byte 0 (Active Low) or SPI Clock Host Write Enable Byte 1 (Active Low) or SPI Data Input
SDRAM Interface
SD_CLK SD_D[31:0] SD_DQM[3:0] SD_A[11:0] SD_BA[1:0] SD_CS_N SD_WE_N SD_RAS_N SD_CAS_N CLK_MII_TX CLK_SSMII_TX MII_TXD[3:0] MII_TX_EN MII_TX_ERR CLK_MII_RX MII_RXD[3:0] MII_RX_DV MII_RX_ERR MII_COL MII_CRS MDC MDIO
Ethernet PHY Interface (MII/RMII/SSMII)
Global Clocks
CLK_SYS_S CLK_SYS CLK_CMN CLK_HIGH
CPU Interface
H_CPU_SPI_N DAT_32_16_N H_D[31:1] H_D[0] / SPI_MISO H_AD[24:1] H_CS_N H_R_W_N / SPI_CP H_WR_BE0_N / SPI_CLK H_WR_BE1_N / SPI_MOSI
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PIN NAME
H_WR_BE2_N / SPI_SEL_N H_WR_BE3_N / SPI_CI H_READY_N H_INT
TYPE
I I Oz O Ipu Ipd Ipu Ipu Oz Ipu I Ipd Ipd I O O O I P P P P P
PIN DESCRIPTION
Host Write Enable Byte 2 or SPI Chip Select (Active Low) Host Write Enable Byte 3 (Active Low) or SPI Clock Invert Host Ready Output (Active Low) Host Interrupt Output. JTAG Test Reset JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output System Reset (Active Low) High Impedance Enable (Active Low) Used for factory tests. Used for factory tests. Used for factory tests. Used for factory tests. Used for factory tests Used for factory tests. Used for factory tests. DS34S104 only. 1.8V Core Voltage for TDM-over-Packet Digital logic (17 pins) 3.3V for I/O Pins (16 pins) Ground for TDM-over-Packet logic and I/O Pins (31 pins) 1.8V for CLAD Analog Circuits Ground for CLAD Analog Circuits
JTAG Interface
JTRST_N JTCLK JTMS JTDI JTDO
Reset and Factory Test Pins
RST_SYS_N HIZ_N SCEN STMD MBIST_EN MBIST_DONE MBIST_FAIL TEST_CLK TST_CLD
Power and Ground
DVDDC DVDDIO DVSS ACVDD1, ACVDD2 ACVSS1, ACVSS2
Note 1: Note 2:
In pin names, the suffix "n" stands for port number: n=1 to 8 for DS34S108; n=1 to 4 for DS34S104; n=2 for DS34S102; n=1 for DS34S101. All pin names ending in "_N" are active low. All pins, except power and analog pins, are CMOS/TTL unless otherwise specified in the pin description. PIN TYPES I = input pin IPD = input pin with internal 50k pulldown to DVSS IPU = input pin with internal 50k pullup to DVDDIO IO = input/output pin IOPD = input/output pin with internal 50k pulldown to DVSS IOPU = input/output pin with internal 50k pullup to DVDDIO O = output pin OZ = output pin that can be placed in a high-impedance state P = power-supply or ground pin
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8 Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. DS34S101, DS34S102 and DS34S108 have a 256-lead thermally enhanced chip-scale ball grid array (TECSBGA) package. The TECSBGA package dimensions are shown in Maxim document 56-G6028-001. DS34S108 has a 484-lead thermally enhanced ball grid array (TEBGA) package. The TEBGA package dimensions are shown in Maxim document 56-G6038-001.
9 Thermal Information
TECSBGA-256 DS34S101 DS34S102 DS34S104 -40 to 85C -40 to 125C 3.7 C/W 13.1 C/W 26.2 C/W TEBGA-484 DS34S108 -40 to 85C -40 to 125C 4.2 C/W 7.1 C/W 16.1 C/W
Parameter Target Ambient Temperature Range Die Junction Temperature Range Theta Jc (junction to top of case) Theta Jb (junction to bottom pins) Theta Ja, Still Air (Note 1)
Note 1: These numbers are estimates using JEDEC standard PCB and enclosure dimensions.
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____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
10 Document Revision History
REVISION DATE 091407 PAGES CHANGED Preliminary release. -- Initial data sheet release. See below for changes made to the data sheet since the 091407 preliminary release version. Removed future status from DS34S104 in the Ordering Information table. 1 DESCRIPTION Updated status of IETF PWE3 standards for CESoPSN and TDMoIP. In Table 9-1 and Table 9-2, corrected the pin type (from Ipd to I) and changed pin description to tell users to connect inputs SCEN and STMD to DVSS. These inputs do not have internal pulldowns. In Section 7.1: Global Features, clarified product and package type relationships for the TEBGA and TECSBGA packages. In Table 9-2, clarified the pin description for input CLK_HIGH, added information for the unused input MCLK. In Table 9-2, changed the output type for H_READY_N to three-stateable (from Opu to Oz). This output does not have an internal pullup. In Table 9-2, simplified the pin descriptions for signals only used in factory (TEST_CLK, SCEN, STMD). In Section 16: Thermal Information, updated the thermal Information for the TEBGA package. Added Theta-JA values for TEBGA deployments with forced air flow. 052908 071808 101708 Removed future status from DS34S108 in the Ordering Information table. Completely revised and simplified. All content derived from the 071108 revision of the full data sheet. Removed all references to AAL2 mode. Corrected some spelling errors and other minor typos. 1, 6, 10, 15 25, 33 14 30 32 33 68 1 All All
040108
Rev: 101708
13 of 13
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